Samsung sticks with its 3nm chips, why doesn’t anyone want them?

The case of Samsung is very curious, because it currently has the most advanced chips in the world and given the growing demand for them, it was to be expected that all designers would run for their share of the manufacturing quota. But the reality is different and rather than running towards them they are fleeing in the opposite direction, but at the beginning of launching it was just the opposite, so what exactly is happening? And why, after the initial boom, neither AMD, nor NVIDIA nor Intel want to know anything? Today we have the main reason exposed, the performance of the Samsung 3nm it is very bad.

Well, the reason is not a problem as such, it is a “problem” for Samsung, to the point that they have had to ask for help because they are not capable of solving it themselves, and this shows that arriving first is not synonymous with success in these hard times in the market.

Samsung’s yield rate per wafer on 3nm with GAA is only 20%

samsung-3-nm-GAA-presentation

Hard as it sounds. The rate of yield of this new lithographic process is only 20%, which is clearly unacceptable, especially for a company like Samsung. This means that of the 100% of the wafers that are recorded with the scanners, only 20% are suitable for use, and also, of that 20%, it will be necessary to see how many high-performance chips can be valid according to the masks and design patterns. of customers.

With this bleak picture, even reaching the market first with this type of transistors, it has been of little use to Samsung, which chains once again another performance issue and back-to-back lagsand for this reason it is not trusted by almost any manufacturer today other than a few daring ones.

It cannot guarantee high-volume production or complex chips and therefore the price cannot be lowered for its customers either, a problem that is being dealt with and observed from the US, since the Koreans have turned to two American companies to to help them

The three types of charge when cutting the chips on a wafer

ESD-Wafer-chip

One of the most common problems with any wafer has to do with electrostatic discharge, or ESD. This occurs when the chips are going to be cut into a wafer with so-called saws, or “Dicers”, to be more technical. When trying to cut the chips, three types of charges are generated that can ruin the engraving on a wafer:

  • frictional load.
  • Spray loading.
  • Separation charge.

The problem with these three types of charges is that the electrification effect is generated by silicon friction, which also produces a deionizing effect, especially in sprinkler charges. For this, in the past in DUV processes three solutions were used for the three types of loads:

  • install a co2 injector to reduce friction.
  • install a ionizer for spraying.
  • suppress radial velocity transfer to the motor arm and thus reduce the capacitance charge by separation, at the cost of course of a longer overall cutting time.

But this is no longer so simple, since the precision and miniaturization of the transistors requires more prior processes to adjust the fault tolerances of one of these three techniques. To avoid these problems that not only generate ESD, you need a software that detects in advance where they occur and knowing this, they are corrected so that once the cut is proceeded, many chips do not die or remain partially unusable.

Silicon Frontline Technology on the scene, can it help Samsung?

ESD-Silicon-Frontline-Technology-ESRA

Well, there are two methods that SFT uses to improve the problems caused by ESD. The first is software known as isra which analyzes in real time the reliability of the wafer to calculate and verify the design of the same, as well as the chips. This process would logically be done before the so-called “silicon test”, which helps to avoid wasting material or time in identifying the problems of each wafer.

This technique is called rmap and simulates the simplified structure of the specific chip, its layers, even its electrical resistance, thereby marking faults and improving resistance by reducing it.

That being said, early results from applying these techniques have improved ESD and Samsung has indicated satisfactory results in the production of chipsalthough he has not commented on how much the percentage improvement has been.

Likewise, they are going to continue working to be able to offer their members a rate of performance in 3nm as expected by samsung, much higher, so Qualcomm, aware of all this in advance, is already in talks with Samsung again to follow up on this problem and its solution. It seems that it will not be fast, but it will be fruitful, let’s hope they can quickly compete with TSMC N5 and Intel 4.

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